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Low Noise/Low Power/2-Wire Bus/256 Taps
Dual Digital Controlled Potentiometers (XDCPTM)
FEATURES Two potentiometers in one package 256 resistor taps-0.4% resolution 2-wire serial interface Wiper resistance: 70 typical @ 3.3V Non-volatile storage of wiper position Standby current < 5A max Power supply: 2.7V to 5.5V 50k, 10k total resistance High reliability --Endurance: 150,000 data changes per bit per register --Register data retention: 50 years @ T 75C * 14-lead TSSOP, 14-pin FCP (Flip-Chip Package) * * * * * * * * * DESCRIPTION
X95820
The X95820 integrates two digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power up the device recalls the contents of the two DCP's IVR to the corresponding WRs. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
2-wire Interface SDA SCL
Power-up, Interface, Control and Status Logic
RH1 WR1 RW1 RL1
A2 A1 A0 Non-Volatile Registers WR0 RH0 RW0 RL0
WP
GND
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PIN CONFIGURATION
TSSOP
VCC WP RH0 RL0 RW0 A2 SCL 1 2 3 4 5 6 7 X95820 14 13 12 11 10 9 8 A1 A0 RH1 RL1 RW1 GND SDA 6789 A2 SCL SDA GND WP RH0 RL0 RW0 2 3 4 5
FCP Bump
VCC A1 14 13 12 11 10 A0 RH1 RL1 RW1
1
ORDERING INFO Ordering Number
X95820WV14I-2.7 X95820UV14I-2.7 X95820WX14I-2.7 X95820UX14I-2.7
Package
14-lead TSSOP 14-lead TSSOP 14-pin Flip-Chip 14-pin Flip-Chip
Resistance Option
10k 50k 10k 50k
PIN ASSIGNMENTS Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Symbol
VCC WP RH0 RL0 RW0 A2 SCL SDA GND RW1 RL1 RH1 A0 A1
Description
Power supply pin Hardware write protection pin. Active low. Prevents any "Write" operation of the 2-wire interface. "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 Device address for the 2-wire interface 2-wire interface clock Serial data I/O for the 2-wire interface Ground "Wiper" terminal of DCP1 "Low" terminal of DCP1 "High" terminal of DCP1 Device address for the 2-wire interface Device address for the 2-wire interface
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ABSOLUTE MAXIMUM RATINGS Storage temperature ..........................-65C to +150C Voltage at any digital interface pin with respect to GND .......................-0.3V to VCC+0.3 VCC .......................................................... -0.3V to +6V Voltage at any DCP pin with respect to GND ..................................... -0.3V to VCC Lead temperature (soldering, 10 seconds) ..........300C IW (10 seconds)................................................... 6mA RECOMMENDED OPERATING CONDITIONS Temp
Industrial
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Min.
-40C
Max.
+85C
Parameter
VCC Power rating of each DCP Wiper current of each DCP
Limits
2.7V to 5.5V
5 mW 3.0 mA
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits Symbol RTOTAL RW CH/CL/CW ILkgDCP INL(6) DNL(5) ZSerror(3) FSerror(4) VMATCH(7) TCV(8) Parameter RH to RL resistance RH to RL resistance tolerance Wiper resistance Potentiometer Capacitance(15) Leakage on DCP pins(15) Integral non-linearity Differential non-linearity Zero-scale error Full-scale error DCP to DCP matching -1 -0.5 0 0 -7 -2 -2 1 0.5 -1 -1 -20 70 10/10/25 0.1 1 1 0.5 7 2 0 0 2 LSB(2) LSB(2) Min. Typ.(1) 10, 50 +20 200 Max. Unit k % pF A LSB(2) LSB(2) LSB(2) Monotonic over all tap positions U option W option U option W option Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals DCP Register set to 80 hex Voltage at pin from GND to VCC VCC = 3.3V @ 25C Wiper current = VCC / RTOTAL Test Conditions W, U versions respectively
Voltage Divider Mode (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)
Ratiometric Temperature Coefficient
4
ppm/C
Resistor Mode (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0 or 1) RINL(12) RDNL(11) Roffset(10) RMATCH(13) TCR(14) Intregal non-linearity Differential non-linearity Offset DCP to DCP Matching Resistance Temperature Coefficient -1 -0.5 0 0 -2 45 1 0.5 1 0.5 7 2 2 MI(9) MI(9) MI(9) MI(9) MI(9) ppm/C Any two DCPs at the same tap position with the same terminal voltages. DCP register set between 20 hex and FF hex DCP register set between 20 hex and FF hex. Monotonic over all tap positions DCP Register set to 00 hex
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X95820
OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.) Limits Typ.1 Max. 1 3 5 2 10
Symbol ICC1 ICC2 ISB ILkgDig
Parameter VCC supply current (Volatile write/read) VCC supply current (nonvolatile write) VCC current (standby) Leakage current, at pins A0, A1, A2, SDA, SCL, and WP pins DCP wiper reponse time Power-on recall voltage VCC ramp rate Power up delay
Min.
-10
Units Test Conditions mA fSCL = 400kHz;SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) mA fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) A VCC = +5.5V, 2 Wire Interface in Standby State A VCC = +3.6V, 2 Wire Interface in Standby State A Voltage at pin from GND to VCC
tDCP(15) Vpor VccRamp tD(15)
1 1.8 0.2 2.6 3
s V V/ms ms
SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs VCC above Vpor, to DCP Initial Value Register recall completed, and 2-Wire Interface in standby state
EEPROM Specs EEPROM Endurance 150,000 EEPROM Retention 50 Serial Interface Specs VIL WP, A2, A1, A0, SDA, and -0.3 SCL input buffer LOW voltage WP, A2, A1, A0, SDA, and 0.7*Vcc VIH SCL input buffer HIGH voltage 0.05* Hysterisis(15) SDA and SCL input buffer hysterisis Vcc SDA output buffer LOW 0 VOL(15) voltage, sinking 4 mA WP, A2, A1, A0, SDA, and Cpin(15) SCL pin capacitance SCL frequency fSCL tIN(15) Pulse width suppression time at SDA and SCL inputs SCL falling edge to SDA tAA(15) output data valid tBUF(15) Time the bus must be free 1300 before the start of a new transmission tLOW Clock LOW time 1300 tHIGH Clock HIGH time 600 tSU:STA START condition setup 600 time tHD:STA START condition hold 600 time tSU:DAT Input data setup time 100
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Cycles Years Temperature 75C 0.3*Vcc V
Vcc+0.3
V
V 0.4 10 400 50 V pF kHz ns
Any pulse narrower than the max spec is suppressed.
900
ns ns
ns ns ns ns ns
SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC
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OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.) (Continued) Limits Typ.1 Max.
Symbol tHD:DAT tSU:STO tHD:STO tDH(15) tR(15) tF(15) Cb(15) Rpu(15)
Parameter Input data hold time STOP condition setup time STOP condition setup time Output data hold time SDA and SCL rise time
Min. 0 600 600 0
20 + 0.1 * Cb SDA and SCL fall time 20 + 0.1 * Cb Capacitive loading of SDA 10 or SCL SDA and SCL bus pull-up 1 resistor off-chip Non-volatile Write cycle time A2, A1, A0, and WP setup time A2, A1, A0, and WP hold time 12 600 600
250 250 400
Test Conditions Units ns From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. ns From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. ns From SDA rising edge to SCL falling edge. Both crossing 70% of VCC. ns From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. ns From 30% to 70% of VCC ns pF k From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF. For Cb = 400 pF, max is about 2~2.5 k. For Cb = 40 pF, max is about 15~20 k
tWP(15) (16) tSU:WPA tHD:WPA
20
ms ns ns Before START condition After STOP condition
SDA vs. SCL Timing
tF SCL tSU:STA SDA (Input Timing) SDA (Output Timing) tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW tR
tAA
tDH
tBUF
WP, A0, A1, and A2 Pin Timing
START SCL Clk 1 STOP
SDA IN tSU:WPA WP, A0, A1, or A2 tHD:WPA
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Notes: (1) Typical values are for TA = 25C and 3.3V supply voltage. (2) LSB: [V(RW)255 - V(RW)0] / 255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. (3) ZS error = V(RW)0 / LSB. (4) FS error = [V(RW)255 - VCC] / LSB. (5) DNL = [V(RW)i - V(RW)i-1] / LSB-1, for i = 1 to 255. i is the DCP register setting. (6) INL = V(RW)i - (i * LSB - V(RW)0) for i = 1 to 255. (7) VMATCH = [V(RWx)i - V(RWy)i] / LSB, for i = 0 to 255, x = 0 to 1 and y = 0 to 1. (8) Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 TC V = --------------------------------------------------------------------------------------------- x ---------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C for i = 16 to 240 decimal, T = -40C to 85C. Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. MI = |R255 - R0| / 255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0 / MI, when measuring between RW and RL. Roffset = R255 / MI, when measuring between RW and RH. RDNL = (Ri - Ri-1) / MI, for i = 32 to 255. RINL = [Ri - (MI * i) - R0] / MI, for i = 32 to 255. RMATCH = (Ri,x - Ri,y) / MI, for i = 0 to 255, x = 0 to 1 and y = 0 to 1.
6
(9) (10) (11) (12) (13)
[ Max ( Ri ) - Min ( Ri ) ] 10 (14) TC = --------------------------------------------------------------- x ---------------R [ Max ( Ri ) + Min ( Ri ) ] 2 125C for i = 32 to 255, T = -40C to 85C. Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. (15) This parameter is not 100% tested. (16) tWC is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a Write sequence of a 2-wire serial interface Write operation, to the end of the selftimed internal non-volatile write cycle.
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GRAPHS
Standby Current vs. Vcc Wiper Resistance vs. Tap Position (Voltage Divider) RL= 0V, RH = Vcc
180 Vcc = 2.7, T = -40C 160 Wiper Resistance () 140 120 100 80 60 40 20 Vcc = 5.5, T = -40C 0 0 50 100 150 200 250 Tap Position (Decimal) Vcc = 5.5, T = 25C 0 2.7 3.2 3.7 4.2 Vcc (V) 4.7 5.2 Vcc = 5.5, T = 85C Standby Current (A) 1.4 1.2 1 -40C 0.8 0.6 0.4 0.2 25C 85C Vcc = 2.7, T = 25C Vcc = 2.7, T = 85C 1.8 1.6
DNL vs. Tap Position in Voltage Divider Mode
0.2 0.15 0.1 DNL (LSB) 0.05 0 -0.05 -0.2 -0.1 -0.15 0 50 100 150 200 250 Tap Position (Decimal) Vcc = 5.5, T = 25C Vcc = 5.5, T = -40C Vcc = 5.5, T = 85C -0.3 -0.4 0 Vcc = 2.7, T = -40C Vcc = 2.7, T = 85C Vcc = 2.7, T = 25C INL (LSB) 0.4 0.3 0.2 0.1 0 -0.1
INL vs. Tap Position in Voltage Divider Mode
Vcc = 5.5, T = 85 C Vcc = 2.7, T = 85 C
Vcc = 2.7, T = -40 C Vcc = 2.7, T = 25 C Vcc = 5.5, T = -40 C Vcc = 5.5, T = 25 C 50 100 150 200 250
Tap Position (Decimal)
ZSerror vs. Temperature
0.4 0 -0.1 0.35 Vcc = 2.7V 0.3
FSerror (LSB)
ZSerror (LSB)
FSerror vs. Temperature
-0.2 Vcc = 5.5V -0.3 -0.4 -0.5 -0.6 -0.7 Vcc = 2.7V
0.25 Vcc = 5.5V 0.2
-0.8 -0.9
0.15 -40
-20
0
20 Temperature (C)
40
60
80
-1 -40 -20 0 20 40 60 80
Temperature (C)
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PRINCIPLES OF OPERATION The X95820 in as integrated circuit incorporating two DCPs with their associated registers, non-volatile memory, and a 2-wire serial interface providing direct communication between a host and the potentiometers and memory. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR of a DCP contains all ones (WR<7:0>: FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the X95820 is being powered up, all two WRs are reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. Soon after the power supply voltage becomes large enough for reliable nonvolatile memory reading, the X95820 reads the value stored on two different non-volatile Initial Value Registers (IVRs) and loads them into their corresponding WRs. The WRs and IVRs can be read or written directly using the 2-wire serial interface as described in the following sections. Memory Description The X95820 contains eight non-volatile bytes. they are accessed by 2-wire interface operations with Address Bytes 0 through 7 decimal. The first two non-volatile bytes at addresses 0 and 1 contain the initial value loaded at power-up into the volatile Wiper Registers (WRs) of DCP0 and DCP1 respectively. Bytes at addresses 2, 3, 4, 5, and 6 are available to the user as general purpose registers. The byte at address 7 is reserved; the user should not write to it, and its value should be ignored if read. The volatile WR, and the non-volatile Initial Value Register (IVR) of a DCP are accessed with the same Address Byte. A volatile byte at address 8 decimal, controls what byte is read or written when accessing DCP registers: the WR, the IVR, or both. When the byte at address 8 is all zeroes, which is the default at power up: - A read operation to addresses 0 or 1 outputs the value of the non-volatile IVRs. - A write operation to addresses 0 or 1 writes the same value to the WR and IVR of the corresponding DCP. When the byte at address 8 is 80h (128 decimal): - A read operation to addresses 0 or 1 outputs the value of the volatile WR. - A write operation to addresses 0 or 1only writes to the corresponding volatile WR. It is not possible to write to an IVR without writing the same value to its corresponding WR. 00h and 80h are the only values that should be written to address 8. All other values are reserved and must not be written to address 8. To access the general purpose bytes at addresses 2, 3, 4, 5, or 6, the value at address 8 must be all zeros. The X95820 is pre-programed with 80h in the two IVRs. Table 1. Memory Map Address
8 7 6 5 4 3 2 1 0
Non-Volatile
-- General Purpose Reserved
Volatile
Access Control Not Available
IVR1 IVR0
WR1 WR0
WR: Wiper Register, IVR: Initial value Register.
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2-WIRE SERIAL INTERFACE The X95820 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the X95820 operates as a slave device in all applications. All communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. See Figure 1. On power up of the X95820 the SDA pin is in the input mode. All 2-wire interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X95820 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met. See Figure 1. A START condition is ignored during the power up sequence and during internal non-volatile write cycles. All 2-wire interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 1. A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 2. The X95820 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The X95820 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation. See Table 2. Table 2. Identification Byte Format
Logic values at pins A2, A1, and A0 respectively
1 (MSB)
0
1
0
A2
A1
A0
R/W (LSB)
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Figure 1. Valid Data Changes, Start, and Stop Conditions
SCL
SDA
START
DATA DATA DATA STABLE CHANGE STABLE
STOP
Figure 2. Acknowledge Response from Receiver
SCL from Master
1
8
9
SDA Output from Transmitter
High Impedance
SDA Output from Receiver START
High Impedance
ACK
Figure 3. Byte Write Sequence
Write Signals from the Master S t a r t Identification Byte Address Byte Data Byte S t o p
Signal at SDA Signals from the X95820
1 0 1 0 A2 A1 A0 0
A C K
0000
A C K A C K
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WRITE OPERATION A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the X95820 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the X95820 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the X95820 enters its standby state. See Figure 3. The byte at address 00001000 bin (8 decimal) determines if the Data Byte is to be written to volatile and/ or non-volatile memory. See "Memory Description" on page 3. DATA PROTECTION The WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW) the device ignores Data Bytes of a Write Operation, does not respond to the Data Bytes with an ACK, and instead, goes to its standby state waiting for a new START condition. A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0, 1, or 8 decimal, the Data Byte is transferred to the appropriate Figure 4. Read Sequence
Signals from the Master S t a r t Identification Byte with R/W=0 S t a r t Identification Byte with R/W=1 S t o p
Wiper Register (WR) or to the Access Control Register, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is between 0 and 6 (inclusive), and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory. READ OPERATION: A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 4). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the X95820 responds with an ACK. Then the X95820 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eigth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte. See Figure 4. The Data Bytes are from the memory location indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 01Fh (8 decimal) the pointer "rolls over" to 00h, and the device continues to output data for each ACK received. The byte at address 00001000 bin (8 decimal) determines if the Data Bytes being read are from volatile or non-volatile memory. See "Memory Description" on page 3.
Address Byte
A C K
A C K
Signal at SDA Signals from the Slave
10 10
0
A C K A C K
10 10
1
A C K First Read Data Byte Last Read Data Byte
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FCP PACKAGING INFORMATION
a d
5 6 7 8 9
4
3 1
2
DIE ID
b
14 10 11 12 13
f e c
Min. Symbol Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter a b c d e f 1.760 1.990 0.785 0.700 0.085 0.110
Nominal Millimeters 1.790 2.020 0.825 0.725 0.100 0.125
Max
1.810 2.050 0.865 0.750 0.115 0.140
Bump Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vcc
X Coordinate, m 725.0 725.0 475.0 225.0 -25.0 -725.0 -725.0 -725.0 -725.0 -126.2 123.8 373.8 629.1 725.0
Y Coordinate, m 535.2 830.0 830.0 830.0 830.0 412.6 162.6 -88.2 -337.4 -830.0 -830.0 -830.0 -830.0 -587.6
WP
RH0 RL0 RW0 A2 SCL SDA vbb! RW1 RL1 RH1 A0 A1
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TSSOP PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.041 (1.05) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
LIMITED WARRANTY
(c)Xicor, Inc. 2004 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, BiasLock and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
REV 1.20 7/28/04
www.xicor.com
Characteristics subject to change without notice.
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